This application claims priority under 35 U.S.C. xc2xa7xc2xa7119 and/or 365 to 9803370-7 filed in Sweden on Oct. 5, 1998; the entire content of which is hereby incorporated by reference.
The present invention relates to a method and to an arrangement for memory management. The method and the arrangement are adapted to manage a first memory and a second memory that operate in parallel with each other, for instance two memories that belong to a first and a second parallel operating processor.
The use of primary memories has long been known to the art. By primary memory is meant in this document a memory that will only retain its information content when a voltage is applied and which will lose: its information content when the voltage is removed, such memories also being designated Random Access Memories (RAMs).
In the case of a memory that coacts with a processor, it is also known to allow respective memories to be accessed for reading and/or writing purposes, through the medium of a connection referred to here as a memory bus, and in time slots that are correlated within instruction cycles associated with the execution work of the processors.
With respect to high reliability requirements of a system, it is also known to allow two mutually different processors to perform the same tasks in parallel with one another, so as to generate redundancy in the system. In such contexts, these processors can be referred to as an executing processor and a stand-by processor.
It is also known in such contexts that the memory or memories that coacts/coact with one processor shall contain the same information as the memory or memories that coacts/coact with the other processor. Since writing of information into the memories and reading of information therefrom can be at fault, it is also known to check parts of the memory content or the whole of said memory content continuously during operation of the processors, for instance by comparing the memory content on the executing side with the memory content on the stand-by side.
When large memories are concerned, the work involved is relatively capacity demanding, and consequently it is usual to check solely the memory content that is most important with respect to the work carried out by the processors.
It is also known when starting up one processor, for instance after a crash, after a service, or after upgrading one processor, to go through a start-up phase which comprises, inter alia, transferring the content of the memory/memories belonging to the still operating processor to the memory/memories belonging to the start-up processor.
The process of reading from one memory and writing into the other memory is capacity demanding and means that the processor will not be available for ordinary working purposes for some time.
It is also known that certain types of work data require uninterrupted processing, such as certain telecommunications applications.
It is also known to vary the load in telecommunications applications with time, and consequently applications that require uninterrupted processing are often allocated a processor capacity that is adapted to handle the highest load that occurs.
Moreover, the capacity requirement can change with respect to a given application, either: increase or decrease, and it is known to upgrade processor capacity in accordance with the new capacity requirements on such occasions.
When considering the earlier standpoint of techniques as described above, it will be seen that a technical problem resides in enabling a given memory to be managed without taking the capacity from the ordinary or standard tasks of the processor in the case of parallel operating processors and their respective primary memories
Another technical problem is one of enabling a start-up phase, for instance in conjunction with service, upgrading, or a re-start after a crash of one processor and its associated memory, while the other processor continues to operate with undiminished capacity with respect to its ordinary tasks.
Another technical problem is one of enabling the memory content of one memory belonging to the operating processor to be transferred to another memory belonging to the start-up processor with undiminished capacity of the working processor in handling its ordinary tasks.
Another technical problem is one of handling changes that occur in the memory of the still operating processor in a manner so that the memory belonging to the start-up processor will also include the changed memory content.
In normal parallel operation between the two processors, another technical problem is one of checking continuously that the parallel operating memories have the same memory content without taking capacity from the ordinary working tasks of the processor to this end.
A further technical problem is one of providing the measures and means required to be able to use empty time slots on a memory bus acting between a processor and a memory for tasks other than the ordinary tasks of a processor.
With the intention of solving one or more of the aforesaid technical problems, the present invention takes as its starting point a memory managing method where a first and a second memory operate in parallel, such as two memories belonging to first and second parallel operating processors, where respective memories are accessed for reading and/or writing purposes via a so-called memory bus and in time slots correlated with instruction cycles associated with the execution work of the processors, and where the second memory shall contain the same information as the first memory.
With a starting point from such a method and with the intention of providing memory managing that does not take the capacity from the ordinary tasks of the processors, it is proposed in accordance with the invention that memory managing includes the detection of empty time slots in the memory bus, and that requisite memory managing is solely carried out in the detected empty time slots.
This means that during a start-up phase, which includes writing the content of the first memory into the second memory in conjunction with a new start or a re-start of the second processor and therewith the second memory, a memory content belonging to a first memory address in the first memory is read, in accordance with the invention, from the first memory and written to a corresponding memory address in the second memory in a first detected empty time slot.
The memory content belonging to a second memory address in the first memory is then read from the first memory and written to a corresponding memory address in the second memory in a second detected empty time slot, and so on until the memory content of the second memory is the same as the memory content in said first memory.
In order to enable the start-up phase to take place during continued operation of the first processor and to enable information to be written into the first memory to be processed under such conditions during the start-up phase, it is proposed in accordance with the invention that writing of information into memory addresses that have already been read and that belong to the first memory also takes place to the second memory during the start-up phase.
With the intention of further simplifying this managing process, it is proposed in accordance with the invention that all writing to a memory address in the first memory also takes place to a corresponding memory address in the second memory during the start-up phase.
When memory managing during normal parallel operation of the first and second processors also includes checking continuously that the whole or parts of the content of the second memory is the same as corresponding parts of the first memory, it is proposed in accordance with the invention that normal operation will also include detection of empty time slots in the memory bus, so as to enable said check to be carried out without using time slots from the ordinary tasks of the memory bus, and to check the memory content only during detected empty time slots.
Respective memories have related means which during a present time slot indicate whether or not the following time slot is empty. With the intention of enabling following empty time slots to be detected, it is proposed in accordance with the invention that this detection is effected by a check carried out by said means.
The present invention also includes a memory management arrangement adapted to operate in accordance with the aforesaid method.
Such an arrangement includes a first and a second memory which are adapted to operate in parallel, such as two memories belonging to respective first and second parallel operating processors, and a memory managing unit adapted to manage said two memories, wherein respective memories are adapted for reading and/or writing access via a so-called memory bus and in time slots correlated with instruction cycles pertaining to the execution work of said processors.
The second memory is adapted to contain the same information as the first memory.
According to the present invention, the arrangement includes a detecting unit which functions to detect empty time slots in the memory bus. The memory managing unit is also adapted to manage the memory solely in said detected empty time slots.
During a start-up phase in conjunction with a new start or a re-start of the second processor and therewith the second memory, the memory managing unit functions to write the memory content of the first memory into the second memory, by reading a memory content belonging to a first memory address in the first memory and writing said memory content to a corresponding memory address in the second memory in one of the empty time slots first detected by the detecting unit.
Similarly, the memory managing unit is adapted to read a memory content belonging to a second memory address in the first memory and write the memory content to a corresponding memory address in the second memory in one of the other empty time slots detected by the detecting unit, and so on until the memory content of said second memory is the same as the memory content of said first memory.
When the first processor is adapted to operate continuously during the start-up phase, the memory managing unit will function to write all that has been written to memory addresses that have already been read in the first memory to corresponding memory addresses in the second memory.
In this case, it is necessary to check which addresses have been read and those which have not been read. With the intention of simplifying memory management and avoiding the necessity of checking which addresses have been read, the inventive memory managing unit can be adapted to write everything that is written to a memory address in the first memory to a corresponding memory address in the second memory during a start-up phase.
When the memory management unit includes a checking unit which functions to check continuously that the whole of the memory content of the second memory or parts of said memory content is the same as corresponding parts of the first memory during normal parallel operation of the first and second processors, it is proposed in accordance with the invention that the checking unit is adapted to operate solely during the empty time slots detected by the detecting unit.
The present invention can build upon an arrangement that includes first means related to the first memory and second means related to the second memory, said means being adapted to show during a present time slot whether or not the next following time slot will be empty, as the processors operate.
In the case of such an arrangement, it is proposed in accordance with the invention that the detecting unit is adapted to detect empty time slots, by checking whether or not the next following time slot is empty through the medium of said means, therewith enabling it to be shown during a present time slot whether or not the next following time slot is empty.
A means of this nature may include a first flip-flop adapted to show whether or not writing into the memory related to said means will take place during the next following time slot, and a second flip-flop adapted to show whether or not reading from a memory related to said means will take place during the next following time slot and that the status of these flip-flops can be read by the detecting unit in accordance with the invention.
In respect of two parallel operating memories belonging to two parallel operating processors and in respect of starting up one of said processors and its memory, the advantages afforded by the inventive method and an inventive arrangement reside in enabling the memory of the start-up processor to be updated without needing to stop the working processor during said update and while enabling the memory bus for ordinary tasks carried out by the working processor to be fully accessed.
In normal parallel operation of the two processors, the present invention also enables the entire memory content, or selected parts of the memory content, of the two parallel operating memories to be checked continuously with full access to the memory bus for standard tasks carried out by the parallel operating processors.
The primary characteristic features of an inventive method are set forth in the characterising clause of the accompanying claim 1, while the primary characteristic features of an inventive arrangement are set forth in the characterising clause of the accompanying Claim 6.